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IEEE 2009 VLSI PROJECT TITLES |
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| VLSI01 |
A Dual-Purpose Real/Complex Logarithmic Number System ALU |
IEEE 2009 |
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| VLSI02 |
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications |
IEEE 2009 |
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| VLSI03 |
An Asynchronous Field-Programmable VLSI using LEDR/4-Phase-Dual-Rail Protocol Converter |
IEEE 2009 |
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| VLSI04 |
Design and FPGA Implementation of High Speed, Low Power Digital Up Converter for Power Line Communication Systems |
IEEE 2009 |
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| VLSI05 |
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters |
IEEE 2009 |
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| VLSI06 |
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations |
IEEE 2009 |
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| VLSI07 |
Efficient Asynchronous Protocol Efficient Asynchronous Protocol Converters for Two Converters for Two-Phase Delay Phase Delay- Insensitive Global Communication |
IEEE 2009 |
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| VLSI08 |
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating |
IEEE 2009 |
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| VLSI09 |
On the Exploitation of Narrow-Width Values for Improving Register File Reliability |
IEEE 2009 |
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| VLSI10 |
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NOC |
IEEE 2009 |
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| VLSI11 |
Low-Power, High-Speed Transceivers for Network-on-Chip Communication |
IEEE 2009 |
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| VLSI12 |
Low-Power Programmable FPGA Routing Circuitry |
IEEE 2009 |
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| VLSI13 |
Design and Implementation of a Field Programmable CRC Circuit Architecture |
IEEE 2009 |
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| VLSI14 |
Scalable Multi-Input–Multi-Output Queues With Application to Variation-Tolerant Architectures |
IEEE 2009 |
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| VLSI15 |
Fault Secure Encoder and Decoder for Nano Memory Applications |
IEEE 2009 |
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| VLSI16 |
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment |
IEEE 2009 |
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| VLSI17 |
Multi-Gb/s LDPC Code Design and Implementation |
IEEE 2009 |
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| VLSI18 |
High-Throughput Layered LDPC Decoding Architecture |
IEEE 2009 |
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| VLSI19 |
Custom Floating-Point Unit Generation for Embedded Systems |
IEEE 2009 |
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| VLSI20 |
An improved RC6 algorithm with the same structure of encryption and decryption |
IEEE 2009 |
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| VLSI21 |
Left to Right Serial Multiplier for Large Numbers on FPGA |
IEEE 2009 |
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| VLSI22 |
Superscalar Power Efficient Fast Fourier Transform FFT Architecture |
IEEE 2009 |
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| VLSI23 |
A New High-Speed Architecture for Reed-Solomon Decoder |
IEEE 2009 |
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| VLSI24 |
Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits |
IEEE 2009 |
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| VLSI25 |
Hardware Algorithm for Variable Precision Multiplication on FPGA |
IEEE 2009 |
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| VLSI26 |
A Compact AES Encryption Core on Xilinx FPGA |
IEEE 2009 |
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| VLSI27 |
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique |
IEEE 2009 |
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